Understanding The Power System

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Understanding The Power System

This video shows you what resistive, inductive, and capacitive phasors look like so that you can start applying realistic faults into relays to guarantee they operate without changing settings.
 

 
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Chris,

What happened to video S1-7-05 or at least your discussion on setting prefault conditions?

Chris Werstiuk (Administrator) October 16, 2016 at 3:33 pm

Hi Shaun,

This was the video on prefault. You can simulate prefault by applying a realistic three-phase balanced condition with a lagging current on all three phases between 10-30 degrees. However, that would mean that you will have to do some phasor and maybe some sequence component math when you’re calculating your trip values. This can cause problems when you solve for fault impedance in a test, for example, and the relay is actually using positive sequence impedance.

Most relay testers apply balanced three phase voltage to prime the relay and remove logic functions like LOP; but they leave the currents at zero so that don’t have to do any math, or know what formula to use because most equations balance out. For example;

A phase to ground fault with no prefault, I residual = A Phase current.
A phase to ground with some prefault current, I residual = Ia, Ib, Ic added vectorally

Joshua Liuga Suiramo February 12, 2021 at 3:43 pm

Hi,

what is the behavior of capacitive and inductive of a cable when a fault(3 ph, 1 ph-neutral & ph-ph, 2 ph-netral/grough) occurs on the line?

Thanks
Joshua

Chris Werstiuk (Administrator) February 13, 2021 at 8:27 am

Capacitance is considered negligible (0) for conductors less than 50 miles long. For non-zero capacitance, any capacitance beyond the fault would be shorted out, so the apparent capacitance at the relay would appear to drop.

Inductance rises significantly because the magnetic fields of self-inductance and mutual inductance go up when the current rises during a fault. The resistance doesn’t change, so the X/R ratio gets larger, which means the current lags more during a fault.

We cover in this in much more detail in the upcoming Overcurrent Relay Testing Seminar.

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